In order to implement human-computer interfaces such as display monitors and audio outputs, computer systems employ digital-to analog (DAC) circuits, which convert digital vectors or addresses to an analog voltage or current. Additionally, DAC circuits are used in a plethora of applications within integrated circuits (ICs) to control, tune, calibrate, or test larger more complex systems.
Simulations are used to establish a minimum voltage Vmin and a maximum voltage Vmax, as defined by equations (1) and (2), respectively, at a DAC output.Vmin=DAC output with the digital address input minimized  Equation (1); andVmax=DAC output with the digital address input maximized  Equation (2).
These voltages Vmax, Vmin are used to calculate an expected DAC output voltage VOUTEXPECT, as defined by equations (3)-(5), at each digital address value and an expected change in output voltage value between two digital addresses that differ by one bit.VOUTEXPECT=(LSB*BIN2DEC(Digital Address))+Vmin  Equation (3);LSB=(Vmax−Vmin)/MAXSTEPS  Equation (4); andMAXSTEPS=(2N−1), where N=a width of a digital address vector  Equation (5).
Once data for these calculations is taken, the digital address is stepped from its minimum value to its maximum value in one bit increments while measuring the output voltage at each step. An ideal DAC output is a stair-step where each plateau or tread represents a voltage equivalent of a digital address input, and a voltage output rises as the digital address input increments from its lowest value to its highest value.
These calculations are also used to determine three measures of DAC circuit quality: (i) integral non-linearity (INL), as defined by equation (6); (ii) differential non-linearity (DNL), as defined by equation (7); and (iii) monotonicity of the circuit. Illustratively,INL=(VOUTMEASURED−VOUTEXPECT)/LSB  Equation (6); andDNL=(VOUTMEASURED(ADDRESS)−VOUTMEASURED(ADDRESS-1))/LSB  Equation (7).
INL is a measurement of how closely a voltage measurement at a DAC output matches predicted values at each address step, i.e., when a digital address increases by one bit. DNL is a measurement of how closely the measured voltage step between two consecutive addresses matches the ideal LSB step value computed for the DAC measured at each address step. INL and DNL values between +/−1.0 LSB are desirable. The DAC is monotonic when a direction of a DAC output voltage changes in the same direction as the change of a digital address change, i.e., when the digital address increases, the DAC output voltage increases, and vice-versa.
Example DAC circuits include a ladder DAC and R-2R DAC. A ladder DAC includes a series of resistors, e.g., a resistor ladder, placed between an upper reference voltage supply and ground, or alternatively, a lower reference voltage supply. The resistor ladder sinks current between the voltage supply and ground, and acts as a multiple-tap voltage divider. Selection switches at each resistor connection point selectively connect a ladder node to an output node of the DAC based on the digital address. In implementation, the ladder DAC requires at least 2N resistors and 2N selection elements, where N is the number of bits in the digital address. Although ladder DACs provide good INL, DNL and monotonic performance, physical implementations become large, and an effective impedance between the voltage supply, ground, and a DAC output increases as the number of bits increases, thus limiting transient performance.
The R-2R DAC includes a plurality of resistor stacks separated by a separation resistor. Each bit of the digital address determines whether a source terminal of a resistor stack unique to that digital address bit is driven from either the voltage supply or ground, or alternatively, a lower reference voltage supply. A drain of a resistor stack associated with a most-significant-bit (MSB) is connected to the DAC output. In addition, the R-2R DAC includes a resistor stack disposed between ground and a drain of a resistor stack associated with a least-significant-bit.
An R-2R DAC is efficient in its use of resistors and selection elements. More specifically, the number of resistors required is determined by (3*N)+1 and the number of selection elements is determined by 2*N, where N is the number of digital address bits. Thus, R-2R DACs compare favorably to ladder DACs in terms of silicon area and impedance between the voltage supply, ground, and the DAC output, resulting in faster transient response.
Worst case INL and DNL values occur at a half-address switch, e.g., for example, in a 7-bit DAC, the half address switch occurs when a digital address switches from 0111111 to 1000000. This is because of an error between an actual resistance value of the resistor stack, e.g., the resistor stack associated with the MSB, due to device mismatch and an ideal value of the resistor stack. As a result, the error swings a voltage of the DAC in opposite directions at the half address switch. Thus, at the half address switch, the DAC output step may be less than the value expected for the LSB and in some cases, may decrease rather than increasing as expected. Thus, the DAC then becomes non-monotonic at the half-address switch.
Although, R-2R DACs with larger resistors provide desirable INL and DNL performance, the area of the resistors far outweighs the area required to implement selection devices, e.g., transistors, for decode logic of an R-2R DAC. Therefore, the large resistor size is a negative in terms of integration/use in larger analog structures. However, R-2R DACs with a smaller resistor area yield undesirable DNL values. Further, similar to the R-2R DAC with larger resistors, the worst case INL and DNL performance occurs at the half address switch. More specifically, at the half address switch, the R-2R DAC then becomes non-monotonic.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.